1. Field of the Invention
The present invention relates to a circuit technique for designing a LSI, and more particularly to a low power consuming logic circuit which is used as a circuit element on a LSI chip in order to implement a LSI which consumes less power.
2. Background of the Invention
A pass-transistor logic which is a kind of a logic circuit is formed by using a MOS transistor as a selection switch for an input signal, and has been known as a logic circuit which can implement a logic having the same functions with a smaller number of transistors than a CMOS logic that has been used most widely, and which can perform operation at high speed with less power consumption. The characteristics and examples of the circuit have been disclosed in "The white paper concerning a technique of low power consuming LSI (ed. by Nikkei Micro Device, Nikkei B.P. Corp.)", pages 98 to 104.
In the prior art, a logic circuit using the pass-transistor logic has had a structure in which a CMOS inverter 102 is connected behind a pass-transistor logic circuit 101 having a small number of stages as shown in FIG. 6 so as to make a set, the similar set is connected in multistage to implement a desired logic, and a logic signal thus obtained is written to a register 103 provided on the next stage. The register 103 performs writing when an effective write clock signal is input.
FIG. 7 illustrates the circuit structure of FIG. 6 in more detail. In FIG. 7, a most significant carry circuit of a 4-bit full adder is illustrated as an example. In the example of FIG. 7, a circuit in which only two stages of NMOS pass-transistors are connected is used as the pass-transistor logic circuit 101 having a small number of stages. For example, NMOS pass-transistors 111 and 112 are counted as 2 stages. As the number of connection stages is smaller, the voltage of a signal output from a pass-transistor on the final connection stage is changed more rapidly. As the number of the connection stages is increased more, the voltage of the output signal is changed more slowly. The CMOS inverter 102 serves to cause the voltage of the signal output from the pass-transistor logic circuit 101 having a small number of stages to be changed more rapidly. Accordingly, the examples according to the prior art shown in FIGS. 6 and 7 have structures suitable for high-speed operation in which the signal voltage in the circuit can be always changed rapidly because the number of connection stages of the pass-transistors is limited to two or three and the CMOS inverter is provided behind them.
However, in the case where the circuits according to the prior art shown in FIGS. 6 and 7 are used as low power consuming logic circuits, the following problems arise.
In the case where a source voltage and an operating frequency are set to the same conditions, the consumed power of the circuit shown in FIGS. 6 and 7 is influenced by the total numbers of transistors and CMOS inverters in the circuit. As the former, the total number of transistors, is increased, the consumed power also tends to be increased. The reason is that charging and discharging of a parasitic capacitor of the transistor cause large power consumption. Regarding the latter, when a CMOS inverter 102 operates, a short circuit current flows from a +VDD to a GND through a PMOS transistor 121 and an NMOS transistor 122 in the process where the signal voltage is changed. The short circuit current is the cause of the power consumption. As the number of the CMOS inverters is increased, the consumed power is also increased. In the case where a reduction in the power consumption is more important than high-speed operation, it seems to be desirable that CMOS inverters 102, 105 and 107 are removed leaving a CMOS inverter 109 which is provided immediately before a register 103 in the circuits shown in FIGS. 6 and 7. Consequently, it seems that the power consumption can be reduced greatly by reducing the numbers of the transistors and the CMOS inverters. The remaining CMOS inverter 109 is necessary for ensuring the operation of the register 103.
However, the above-mentioned method has omissions to result in an increase in the power consumption, which is caused by the characteristics of the CMOS inverter. As described above, the CMOS inverter outputs an input signal such that the voltage thereof is changed more rapidly. In this case, as the voltage of the input signal is changed slowly, the magnitude of the short circuit current is increased rapidly. In more detail, the short circuit current flows in the CMOS inverter only when the voltage of the signal input to the CMOS inverter has an intermediate value which is neither sufficiently high nor low. For example, the short circuit current flows in the CMOS inverter 102 only when the voltage of the input signal is lower than the threshold voltage of the PMOS transistor 121 and is higher than the threshold voltage of the NMOS transistor 122. Accordingly, as the voltage of the input signal rises or drops slowly, the time for which the voltage of the input signal has the intermediate value is increased rapidly. Consequently, the time for which the short circuit current flows is increased proportionally. As a result, the power consumption is increased.
If the three CMOS inverters are removed by the above-mentioned method, pass-transistor logic circuits 101, 104, 106 and 108 having a small number of stages are directly connected to one another. Consequently, the number of connection stages of NMOS pass-transistors is increased from 2 to 8. As a result, the voltage of a signal output from a pass-transistor provided on the final stage is changed very slowly. This signal is input to the CMOS inverter 109. Consequently, the short circuit current of the CMOS inverter 109 is increased greatly. Thus, the power consumption is increased much more than the effects of power reduction which are obtained by removing the three CMOS inverters.
In order to solve the above-mentioned problems and obtain a low power consuming logic circuit, thus, it is necessary to implement a circuit structure in which a short circuit current having a high magnitude does not flow to a CMOS inverter also in the case where the voltage of the signal input to the CMOS inverter is changed slowly. The present invention has been made to implement this circuit structure.